Log-Free Concurrent Data Structures

Non-volatile RAM (NVRAM) makes it possible for data structures to tolerate transient failures, assuming however that programmers have designed these structures such that their consistency is preserved upon recovery. Previous ap- proaches are typically transactional and inherently make heavy use of logging, resulting in implementations that are significantly slower than their DRAM counterparts. In this paper, we introduce a set of techniques aimed at lock-free data structures that, in the large majority of cases, remove the need for logging (and costly durable store instructions) both in the data structure algorithm and in the associated memory management scheme. Together, these generic techniques enable us to design what we call log-free concurrent data structures, which, as we illustrate on linked lists, hash tables, skip lists, and BSTs, can provide several-fold performance improvements over previous transaction-based implementations, with overheads of the order of milliseconds for recovery after a failure. We also highlight how our techniques can be integrated into practical systems, by presenting a durable version of Memcached that maintains the performance of its volatile counterpart

Statistička analiza rezultata ispitivanja fizičko-mehaničkih svojstava kontrolnih betonskih kocki

Cilj ovog istraživanja je prikupljanje, obrada i statistička analiza rezultata ispitivanja uzoraka betonskih kocki koji su ispitani u Laboratoriji za materijale Građevinskog fakulteta u Beogradu prema standardu SRPS ISO 4012:2000 u periodu od 2012. do 2017. godine. Za potrebe analize, preuzeti su podaci iz Izveštaja o ispitivanju kontrolnih betonskih kocki, prepoznate su i klasifikovane osnovne karakteristike očvrslog betona. Izvršena je statistička analiza datuma betoniranja, starosti uzoraka, sastava betona, zapreminske mase, čvrstoće pri pritisku, zahtevane marke betona itd. Statistika je pokazala da su najčešće upotrebljavani cementi sledećih oznaka: CEM II A-M (V-L), CEM II A-M (S-L), CEM II A-S, a da najveće učešće imaju marke betona MB 30 sa 66,8% i MB 40 sa 14,3% udela

Inhibition of proinflammatory signaling impairs fibrosis of bone marrow mesenchymal stromal cells in myeloproliferative neoplasms

Although bone marrow-derived mesenchymal stromal cells (BM-MSCs) have been identified as a major cellular source of fibrosis, the exact molecular mechanism and signaling pathways involved have not been identified thus far. Here, we show that BM-MSCs contribute to fibrosis in myeloproliferative neoplasms (MPNs) by differentiating into αSMA-positive myofibroblasts. These cells display a dysregulated extracellular matrix with increased FN1 production and secretion of profibrotic MMP9 compared to healthy donor cells. Fibrogenic TGFβ and inflammatory JAK2/STAT3 and NFκB signaling pathway activity is increased in BM-MSCs of MPN patients. Moreover, coculture with mononuclear cells from MPN patients was sufficient to induce fibrosis in healthy BM-MSCs. Inhibition of JAK1/2, SMAD3 or NFκB significantly reduced the fibrotic phenotype of MPN BM-MSCs and was able to prevent the development of fibrosis induced by coculture of healthy BM-MSCs and MPN mononuclear cells with overly active JAK/STAT signaling, underlining their involvement in fibrosis. Combined treatment with JAK1/2 and SMAD3 inhibitors showed synergistic and the most favorable effects on αSMA and FN1 expression in BM-MSCs. These results support the combined inhibition of TGFβ and inflammatory signaling to extenuate fibrosis in MPN

Hermes: a Fast, Fault-Tolerant and Linearizable Replication Protocol

Today's datacenter applications are underpinned by datastores that are responsible for providing availability, consistency, and performance. For high availability in the presence of failures, these datastores replicate data across several nodes. This is accomplished with the help of a reliable replication protocol that is responsible for maintaining the replicas strongly-consistent even when faults occur. Strong consistency is preferred to weaker consistency models that cannot guarantee an intuitive behavior for the clients. Furthermore, to accommodate high demand at real-time latencies, datastores must deliver high throughput and low latency. This work introduces Hermes, a broadcast-based reliable replication protocol for in-memory datastores that provides both high throughput and low latency by enabling local reads and fully-concurrent fast writes at all replicas. Hermes couples logical timestamps with cache-coherence-inspired invalidations to guarantee linearizability, avoid write serialization at a centralized ordering point, resolve write conflicts locally at each replica (hence ensuring that writes never abort) and provide fault-tolerance via replayable writes. Our implementation of Hermes over an RDMA-enabled reliable datastore with five replicas shows that Hermes consistently achieves higher throughput than state-of-the-art RDMA-based reliable protocols (ZAB and CRAQ) across all write ratios while also significantly reducing tail latency. At 5% writes, the tail latency of Hermes is 3.6X lower than that of CRAQ and ZAB.Comment: Accepted in ASPLOS 202

Predicting the Scalability of an STM A Pragmatic Approach

Conducting a thorough performance evaluation of an STM is very time consuming. Depressingly, even with all this effort, and even with the same application, it can still be hard to predict the performance if the number of underlying threads on which the application needs to be deployed is different than those of the experiment. Basically, one might have to conduct an entire set of new experiments to get some understanding of the performance of the STM with the new number of threads. We propose a pragmatic approach to contribute to changing this state of affairs. Using classical engineering approximation techniques, we extract from a set of STM performance measurements, analytical performance functions to model the scalability of the STM. We show, more specifically, that polynomial and rational functions provide good interpolations of STM performance: even with only a handful of measurements, the average error in most cases is around 1-2%. Further, we show that we can perform reasonably precise extrapolation using rational functions: basically, using measurements with up to m threads, we can predict the performance up to roughly 2m threads with a relatively low error (around 10 % in best cases). We discuss two possible applications of our approach: (1) statically deciding whether to use an STM for a given workload and a given number of threads, and (2) dynamically adjusting the number of threads that execute in parallel to match the optimal concurrency level of a given workload

A Pragmatic Approach for Predicting the Scalability of Parallel Applications

Predicting the scalability of parallel applications is becoming crucial now that the number of cores in modern CPUs doubles roughly every two years. Traditional ways to get some understanding of the scalability of a parallel application rely on extensive experiments or detailed application models. Both are very time consuming and often hard to use. This paper presents PreSca, a pragmatic system for predicting the scalability of parallel applications. PreSca uses function approximation techniques to model scalability with an analytical performance function extracted from a set of measurements. By considering the application as a black-box without requiring any knowledge about its internals, PreSca can be applied with little effort to any parallel application. We show how PreSca can be used statically to predict the scalability of a given application and decide which synchronization primitive scales best for it as well as how it can be used on-line to dynamically assist scheduling decisions and adjust core assignment. In some sense, PreSca shows, for the first time, how function approximation can be used to predict the scalability of parallel applications in a completely general way. We extensively evaluated PreSca using a large number of parallel benchmarks, including some that use locks and some that use transactional memory. We also consider two different multicore systems. Our evaluation shows that PreSca produces accurate results. More specifically: (1) PreSca’s interpolations based on only 8 measurements have 90th percentile of error lower than 15%, (2) PreSca’s extrapolations using measurements with up to m cores predict the performance for n ≤ 2m cores with errors lower than 20 % in most cases, and (3) PreSca’s on-line scheduler determines the optimal thread count using fewer than 7 measurements with errors lower than 3 % on average. 1